Difference between revisions of "Main Page"

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* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Verilog ports being renamed | Verilog: Port Expressions]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
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* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
 
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
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* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
 
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
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* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
'''Netlist Database'''
 
'''Netlist Database'''
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'''Code examples'''
 
'''Code examples'''
 
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
 
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
 +
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
 +
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 +
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
 +
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
 
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
 
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
 
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
 
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
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* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 +
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
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* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 +
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
 
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 +
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]

Latest revision as of 22:25, 27 February 2024

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples