Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 48: Line 48:
 
* [[Extract clock enable | Database: Extract clock enable]]
 
* [[Extract clock enable | Database: Extract clock enable]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog: Retrieve package name for user-defined variable types]]
 +
* [[Pretty-print a module and the packages imported by the module | SystemVerilog: Pretty-print a module and the packages imported by the module]]

Revision as of 16:12, 1 March 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples