Difference between revisions of "Main Page"

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* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++: Retrieve package name for user-defined variable types]]
+
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++/Python: Pretty-print a module and the packages imported by the module]]
+
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 12:02, 9 April 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples