Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 77: Line 77:
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 +
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]

Revision as of 12:36, 27 July 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples