Difference between revisions of "Main Page"

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'''VHDL, Verilog, Liberty, EDIF'''
 
'''VHDL, Verilog, Liberty, EDIF'''
* [[ VHDL,_Verilog,_Liberty,_EDIF#AllFilesVY | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
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* [[I'm using -v, -y, | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[ VHDL,_Verilog,_Liberty,_EDIF#NetlistWhichModule | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]]
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* [[While looking at a Netlist | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]]
* [[ VHDL,_Verilog,_Liberty,_EDIF#PortsRenamedP1P2 | Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Why are the ports | Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[ VHDL,_Verilog,_Liberty,_EDIF#VrlgOrSV | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
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* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
* [[ VHDL,_Verilog,_Liberty,_EDIF#VHDL9308 | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
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* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
  
  

Revision as of 17:08, 8 July 2016

General


VHDL, Verilog, Liberty, EDIF




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