Difference between revisions of "Main Page"

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'''General'''
 
'''General'''
 +
* [[How to make lives easier | How to make lives easier]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]

Revision as of 17:45, 4 July 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples