Difference between revisions of "Main Page"

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* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[test-based design modification | Verilog/C++: test-based design modification]]  
+
* [[Test-based design modification | Verilog/C++: Test-based design modification]]  
 
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]

Revision as of 14:33, 19 July 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples