Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 32: Line 32:
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
 +
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]

Revision as of 14:37, 4 October 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples