Difference between revisions of "Main Page"

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* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName]]
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* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
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* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 15:54, 21 January 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples