Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 42: Line 42:
 
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
 
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
 
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
 
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
 +
* [[System attributes | Netlist Database: System attributes]]
 
'''Output'''
 
'''Output'''
 
* [[Output file formats | What language formats does Verific support as output?]]
 
* [[Output file formats | What language formats does Verific support as output?]]

Revision as of 14:27, 13 February 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples