Difference between revisions of "Main Page"

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* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
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* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
 
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]

Revision as of 11:10, 19 April 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples