Difference between revisions of "Main Page"

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* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 +
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]

Revision as of 16:00, 19 April 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples