Difference between revisions of "Main Page"

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* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree : How to detect multiple-clock-edge condition in Verilog parsetree]]
+
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]

Revision as of 10:43, 9 June 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples