Difference between revisions of "Main Page"

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* [[LineFile data from input files | LineFile data from input files]]
 
* [[LineFile data from input files | LineFile data from input files]]
 
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
 
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets | Preserving user nets - preventing nets from being optimized away]]
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* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
  
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''

Revision as of 11:26, 1 April 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples