Difference between revisions of "Main Page"

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* [[General]]
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General
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* [[How do I know what language a Netlist in the netlist database comes from?]]
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* [[What are the data structures in Verific?]]
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* [[Does Verific support cross module references (XMR)?]]
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* [[VHDL, Verilog, Liberty, EDIF]]
 
* [[VHDL, Verilog, Liberty, EDIF]]
 
* [[Output]]
 
* [[Output]]
 
* [[TCL, Perl, Python, Java]]
 
* [[TCL, Perl, Python, Java]]

Revision as of 13:40, 7 July 2016

General