Difference between revisions of "Main Page"
From Verific Design Automation FAQ
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* [[General | How do I know what language a Netlist in the netlist database comes from?]] | * [[General | How do I know what language a Netlist in the netlist database comes from?]] | ||
* [[General | What are the data structures in Verific?]] | * [[General | What are the data structures in Verific?]] | ||
| − | * [[General | Does Verific support cross module references (XMR)?]] | + | * [[General:XMR | Does Verific support cross module references (XMR)?]] |
* [[VHDL, Verilog, Liberty, EDIF]] | * [[VHDL, Verilog, Liberty, EDIF]] | ||
* [[Output]] | * [[Output]] | ||
* [[TCL, Perl, Python, Java]] | * [[TCL, Perl, Python, Java]] | ||
Revision as of 14:03, 7 July 2016
General
