Difference between revisions of "Notes on analysis"
From Verific Design Automation FAQ
| Line 11: | Line 11: | ||
* removes include directories | * removes include directories | ||
* processes root module | * processes root module | ||
| − | * undefines user-defined macros | + | * undefines user-defined macros, including command-line macros |
* resets compile directives (e.g. `default_nettype, `timescale) | * resets compile directives (e.g. `default_nettype, `timescale) | ||
Revision as of 11:38, 26 January 2022
First, please read this article: Defined macros become undefined - MFCU vs SFCU.
Q: Can I use veri_file::Analyze() to read SystemVerilog input files one by one, all of them belonging to one compilation unit?
Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().
veri_file::AnalyzeMultipleFiles(), besides analyzing each file, also:
- opens and ends the compilation unit
- processes –v and –y options
- removes include directories
- processes root module
- undefines user-defined macros, including command-line macros
- resets compile directives (e.g. `default_nettype, `timescale)
If you use veri_file::Analyze() to analyze files one by one, you’ll need to call these APIs to complete the analysis before starting any other operations:
- veri_file::ProcessUserLibraries()
- veri_file::RemoveAllIncludeDirs()
- veri_file::EndCompilationUnit()
The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.
