Notes on analysis

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First, please read this article: Defined macros become undefined - MFCU vs SFCU.

>> Can I use veri_file::Analyze) to read System Verilog input files one by one, all of them belonging to one compilation unit?

Yes. But if you have multiple files, it’s better to use veri_file::AnalyzeMultipleFiles().

veri_file::AnalyzeMultipleFiles(), besides analyzing each files, also:

  • opens and ends the compilation unit
  • processes –v and –y options
  • removes include directories
  • processes root module
  • undefines user-defined macros
  • resets compile directives (e.g. `default_nettype, `timescale)

If you use veri_file::Analyze() to analyze files one by one, you’ll need to call these APIs to complete the analysis before starting any other operations:

  • veri_file::ProcessUserLibraries()
  • veri_file::RemoveAllIncludeDirs()
  • veri_file::EndCompilationUnit()