Output file formats
From Verific Design Automation FAQ
Revision as of 18:34, 22 July 2016 by Hoa (Talk | contribs) (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...")
Q: What language formats does Verific software support as output?
Verific software can write out:
- RTL Verilog/SystemVerilog (from parsetree)
- RTL VHDL (from parsetree)
- Structural Verilog (from netlist database)
- Structural VHDL (from netlist database)
- BLIF (from netlist database)
- EDIF (from netlist database)
