Process -f file and explore the Netlist Database (py)

#!/usr/bin/python

import sys
import re
sys.path.append('../../../pythonmain/install')
import Verific
def Accumulate(netlist,done):
    if not netlist: 
        return
    if done.GetItem(netlist):
        return 
    # foreach_instance_in_netlist
    insts = Verific.InstanceMapIter(netlist.GetInsts())
    inst = insts.First()
    while (inst):
        Accumulate(inst.View(),done)
        inst = insts.Next()
    done.Insert(netlist)

def PrintInstances(netlist):
    if not netlist:
        # ignore NULL netlists
        return
    if not netlist.IsUserDeclared():
        # Ignore Verific operators and primitives
        return
    insts = Verific.InstanceMapIter(netlist.GetInsts())
    inst = insts.First()
    while (inst):
        if inst.IsUserDeclared():
            name = inst.Name()
            two = inst.View().Owner().Name()
            print (("Instance %s of module %s") % (inst.Name(), inst.View().Owner().Name()))
        inst = insts.Next()
    

def PrintInterface(netlist):
    if not netlist:
        return
    if not netlist.IsUserDeclared():
        return
    ports = Verific.PortMapIter(netlist.GetPorts())
    port = ports.First()
    while (port):
        if (port.Bus()):
            port = ports.Next()
            continue
        if (port.IsInout()):
            print ("Inout port %s" % port.Name())
        if (port.IsOutput()):
            print ("Output port %s" % port.Name())
        if (port.IsInput()):
            print ("Input port %s" % port.Name())
        port = ports.Next()
    port_buses = Verific.PortBusMapIter(netlist.GetPortbuses()) 
    port_bus = port_buses.First();
    while (port_bus):
        if (port_bus.IsInout()):
            print (("Inout port_bus %s[%d:%d]") % (port_bus.Name(), port_bus.LeftIndex(), port_bus.RightIndex()))
        if (port_bus.IsOutput()):
            print (("Output port_bus %s[%d:%d]") % (port_bus.Name(), port_bus.LeftIndex(), port_bus.RightIndex()))
        if (port_bus.IsInput()):
            print (("Input port_bus %s[%d:%d]") % (port_bus.Name(), port_bus.LeftIndex(), port_bus.RightIndex()))
        port_bus = port_buses.Next()

verilog_reader = Verific.veri_file()

f_file = "files.f"

# NO_MODE: mode keyed off the file dialect - MFCU Verilog 2000 and SFCU for SystemVerilog
cu_mode = verilog_reader.NO_MODE

# UNDEFINED: dialect keyed off the file extension - .v for Verilog 2000 and .sv for SystemVerilog
f_analysis_mode = verilog_reader.UNDEFINED

# can use verilog_reader.F_FILE_NONE or verilog_reader.F_FILE_CAPITAL
file_names = Verific.PythonProcessFFile(f_file, verilog_reader.F_FILE_NONE, f_analysis_mode)

file_names = Verific.StringArrayIter(file_names)
file_name = file_names.First()
parsed_files  = [] # container for all files that end in .v or .sv
while (file_name):
    file_ok = 0
    if (re.search("\.v$", file_name)):
        parsed_files.append(file_name)
        file_ok = 1
    if (re.search("\.sv$", file_name)):
        parsed_files.append(file_name)
        file_ok = 1
    if not file_ok:
        print ("File %s has invalid extension - ignored.\n" % file_name)
    file_name = file_names.Next()
 
# Next, check whether the analysis mode is set from -f file: 
if f_analysis_mode == verilog_reader.UNDEFINED:
    # default to Verilog 2001:
    f_analysis_mode = verilog_reader.VERILOG_2K
    # but treat .sv files as SystemVerilog
    verilog_reader.AddFileExtMode(".sv", verilog_reader.SYSTEM_VERILOG)

# Analysis
for file_name in parsed_files:
    if not verilog_reader.Analyze(file_name, f_analysis_mode, "work", cu_mode):
        print ("Analyze failure. Exiting")
        sys.exit(1)

# elaboration
Verific.RuntimeFlags_SetVar("veri_ignore_always_constructs",1)
if not verilog_reader.ElaborateAll("work"):
    print ("Elaboration error. Exiting")
    sys.exit(1)

# exploring the netlist database
top = Verific.Netlist_PresentDesign()

linefile_info_filename = Verific.LineFile_GetFileName(top.Linefile())
linefile_info_line_no = Verific.LineFile_GetLineNo(top.Linefile())
owner_name = top.Owner().Name()
top_name = top.Name()

print ("%s(%s): INFO: top level design is %s(%s)" % (linefile_info_filename, linefile_info_line_no, owner_name, top_name))

set_of_netlists = Verific.Set()

Accumulate(top, set_of_netlists)

netlists = Verific.NetlistSetIter(set_of_netlists)
netlist = netlists.First()
while (netlist):
    if not netlist.IsUserDeclared():
        netlist = netlists.Next()
        continue
    lf_filename = Verific.LineFile_GetFileName(netlist.Linefile())
    lf_line_no  = Verific.LineFile_GetLineNo(netlist.Linefile())
    if lf_filename and lf_line_no:
        print("\n%s(%s): INFO: module %s was instantiated %d times" % (lf_filename, lf_line_no, netlist.Owner().Name(), netlist.NumOfRefs())) 
    else:
        print("\nINFO: module %s was instantiated %d times" % (netlist.Owner().Name(), netlist.NumOfRefs())) 
    PrintInterface(netlist)
    PrintInstances(netlist)
    netlist = netlists.Next()    

sys.exit(0)