Difference between revisions of "Retrieve package name for user-defined variable types"

Latest revision as of 12:03, 9 April 2019

C++ source:

#include <iostream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"
#include "VeriId.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class VdpVisitor : public VeriVisitor
{
public:
    VdpVisitor() : VeriVisitor() { }
    virtual ~VdpVisitor() { }

    void VERI_VISIT(VeriAnsiPortDecl, node)
    {
        VeriDataType *dt = node.GetDataType() ;

        VeriIdDef *id;
        unsigned i;
        FOREACH_ARRAY_ITEM(node.GetIds(), i, id) {
            if (!id || !id->IsPort()) continue ;
            if (dt && dt->IsTypeRef()) {
                VeriName *tn = dt->GetTypeName() ;
                if (!tn) continue ;
                // Method 1:
                cout << tn->GetPrettyPrintedString() << endl ;
                // Method 2:
                VeriName *prefix = (tn->IsScopeName()) ? tn->GetPrefix() : 0 ;
                if (prefix) cout << prefix->GetName() << "::" ;
                cout << tn->GetName() << endl ;
            }
        }
    }
} ; // class VdpVisitor

int main(int argc, const char **argv)
{
    const char *file = (argc > 1) ? argv[1] : "test.v" ;
    if (!veri_file::Analyze(file, veri_file::SYSTEM_VERILOG)) return 1 ;

    veri_file::PrettyPrint("test_pp.v.golden.new", 0) ;

    VeriModule *test = veri_file::GetModule("test") ;
    if (!test) return 2 ;

    VdpVisitor mv ;
    test->Accept(mv) ;

    return 0 ;
}
 

Python script:

#! /usr/bin/python
import sys
sys.path.append('../../../pythonmain/install')
import Verific

class ExampleVisitor(Verific.VeriPythonVisitor):
    def __init__(obj):
        if not obj:
            return

    def VisitVeriAnsiPortDecl(self, node):
        data_type = node.GetDataType()
        ids = Verific.VeriIdDefArrayIter(node.GetIds())
        id = ids.First()
        while (id):
            if (not id.IsPort()): 
                continue
            if (data_type and data_type.IsTypeRef()):
                type_name = data_type.GetTypeName()
                if (not type_name):
                    continue
                # method 1:
                print ("%s" % type_name.GetPrettyPrintedString()) 
                # method 2:
                prefix = 0
                if type_name.IsScopeName:
                    prefix = type_name.GetPrefix()
                if prefix:
                    print ("%s::%s" % (prefix.GetName(),type_name.GetName()))
                else:
                    print ("%s" % type_name.GetName()) 
            id = ids.Next()


# main
reader = Verific.veri_file()
file = "test.v"
if (not reader.Analyze(file, reader.SYSTEM_VERILOG)):
    sys.exit(1)

reader.PrettyPrint("test_pp.v.golden.new", "test")

test = reader.GetModule("test") ;
if (not test):
    sys.exit(2)

visitor = ExampleVisitor()
visitor.Visit(test)

sys.exit(0)
 

Verilog test design:

package answer;
    typedef struct {
        logic [3:0] who;
        logic [3:0] what;
        logic [3:0] where;
    } s;
endpackage: answer
 
package question;
    typedef struct {
        logic [3:0] who;
        logic [3:0] what;
        logic [3:0] where;
    } s;
endpackage: question
 
module test (
    input  question::s  q,
    output answer::s    a
);
endmodule: test

Run:

[hoa@awing0 test]$ ./test-linux 
-- Analyzing Verilog file 'test.v' (VERI-1482)
-- Pretty printing all design elements in all libraries to file 'test_pp.v.golden.new' (VERI-1492)
question::s
question::s
answer::s
answer::s
[hoa@awing0 test]$