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Showing below up to 127 results in range #1 to #127.

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  1. General‏‎ (14:01, 7 July 2016)
  2. VHDL, Verilog, Liberty, EDIF‏‎ (14:23, 7 July 2016)
  3. How do I know what language a Netlist in the netlist database comes from?‏‎ (16:33, 8 July 2016)
  4. Does Verific support cross module references (XMR)?‏‎ (16:35, 8 July 2016)
  5. I'm using -v, -y,‏‎ (17:09, 8 July 2016)
  6. While looking at a Netlist‏‎ (17:10, 8 July 2016)
  7. Why are the ports‏‎ (17:15, 8 July 2016)
  8. I have a design consisting of‏‎ (17:15, 8 July 2016)
  9. A customer wants to analyze/elaborate‏‎ (17:16, 8 July 2016)
  10. How do I know‏‎ (17:36, 8 July 2016)
  11. Does Verific support cross‏‎ (17:37, 8 July 2016)
  12. What are the data‏‎ (12:55, 22 July 2016)
  13. Verific data structure‏‎ (15:35, 22 July 2016)
  14. How to get module ports from Verilog parsetree‏‎ (15:46, 22 July 2016)
  15. Output file formats‏‎ (18:34, 22 July 2016)
  16. Design with VHDL-1993 and VHDL-2008 files‏‎ (12:44, 29 November 2016)
  17. Original RTL language‏‎ (13:20, 8 December 2016)
  18. How to get linefile information of macro definitions‏‎ (16:45, 22 March 2017)
  19. How to find port dimensions‏‎ (14:42, 6 April 2017)
  20. How to identify packages being imported into a module‏‎ (16:47, 11 May 2017)
  21. How to get enums from Verilog parsetree‏‎ (10:36, 14 June 2017)
  22. How to create a Netlist database from scratch (not from RTL input)‏‎ (17:10, 24 August 2018)
  23. Support IEEE 1735 encryption standard‏‎ (11:58, 31 August 2018)
  24. Top level module with interface ports‏‎ (17:41, 28 December 2018)
  25. Design with System Verilog and Verilog 2001 files‏‎ (11:52, 12 February 2019)
  26. Cross-reference between the original RTL files and the elaborated netlist‏‎ (15:30, 15 February 2019)
  27. What languages can I use with Verific software?‏‎ (16:48, 21 February 2019)
  28. Prettyprint to a string‏‎ (13:40, 1 March 2019)
  29. Write out an encrypted netlist‏‎ (13:54, 1 March 2019)
  30. Extract clock enable‏‎ (14:08, 1 March 2019)
  31. Process -f file and explore the Netlist Database‏‎ (17:08, 1 March 2019)
  32. Process -f file and explore the Netlist Database (py)‏‎ (17:14, 1 March 2019)
  33. Process -f file and explore the Netlist Database (C++)‏‎ (17:17, 1 March 2019)
  34. Retrieve package name for user-defined variable types‏‎ (12:03, 9 April 2019)
  35. What are the data structures in Verific?‏‎ (17:25, 9 May 2019)
  36. How to make lives easier‏‎ (18:14, 4 July 2019)
  37. Type Range example‏‎ (16:41, 16 July 2019)
  38. Test-based design modification‏‎ (14:00, 18 July 2019)
  39. Logic optimization across hierarchy boundaries‏‎ (16:19, 22 July 2019)
  40. Comment out a line using test-based design modification and parsetree modification‏‎ (12:21, 14 August 2019)
  41. Getting instances' parameters‏‎ (14:11, 21 August 2019)
  42. How to ignore a (not used) parameter/generic in elaboration.‏‎ (14:55, 4 October 2019)
  43. How to check for errors in analysis/elaboration‏‎ (14:00, 29 January 2020)
  44. Memory elements of a RamNet‏‎ (17:53, 31 January 2020)
  45. Bit-blasting a multi-port RAM instance‏‎ (16:02, 10 February 2020)
  46. Using stream input to ignore input file‏‎ (17:04, 12 February 2020)
  47. Verific data structures‏‎ (16:13, 27 April 2020)
  48. Macro Callback example‏‎ (13:03, 6 May 2020)
  49. What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?‏‎ (13:40, 6 May 2020)
  50. Verilog/C++: How to use IsUserDeclared() and port associations‏‎ (16:13, 13 May 2020)
  51. Verilog/C++: How to use IsUserDeclared() : Example for port associations‏‎ (16:40, 13 May 2020)
  52. How to use RegisterCallBackMsg()‏‎ (14:44, 14 May 2020)
  53. Parsing from data in memory‏‎ (14:12, 1 June 2020)
  54. Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path‏‎ (12:24, 23 June 2020)
  55. How to get full hierarchy ID path‏‎ (12:31, 23 June 2020)
  56. How to create new module in Verilog parsetree‏‎ (13:01, 23 June 2020)
  57. Access attributes of ports in parsetree‏‎ (14:10, 9 July 2020)
  58. Included files associated with a Verilog source file‏‎ (17:06, 22 July 2020)
  59. Simulation models for Verific primitives‏‎ (12:05, 4 September 2020)
  60. Type Range example with multi-dimensional arrays‏‎ (16:07, 13 November 2020)
  61. Hierarchy tree RTL elaboration‏‎ (15:11, 25 February 2021)
  62. Does Verific build CDFG?‏‎ (18:10, 25 February 2021)
  63. Release version‏‎ (18:12, 25 February 2021)
  64. Where in RTL is it get assigned?‏‎ (13:22, 23 March 2021)
  65. Where in RTL does it get assigned?‏‎ (22:42, 30 March 2021)
  66. Visiting Hierarchical References (VeriSelectedName)‏‎ (12:02, 8 April 2021)
  67. Comment out a line using text based design modification and parsetree modification‏‎ (14:17, 8 April 2021)
  68. Fanout cone and grouping‏‎ (20:34, 18 April 2021)
  69. How to get library containing nested module‏‎ (11:52, 19 April 2021)
  70. Buffering signals and ungrouping‏‎ (16:11, 19 April 2021)
  71. Does Verific support XMR?‏‎ (22:46, 20 April 2021)
  72. How Verific elaborator handles blackboxes/unknown boxes‏‎ (16:00, 21 April 2021)
  73. Tcl library path‏‎ (10:46, 27 April 2021)
  74. How to detect multiple-clock-edge condition in Verilog parsetree‏‎ (10:27, 11 June 2021)
  75. Defined macros become undefined - MFCU vs SFCU‏‎ (10:33, 11 June 2021)
  76. Remove Verific data structures‏‎ (15:07, 23 June 2021)
  77. Accessing and evaluating module's parameters‏‎ (13:14, 27 July 2021)
  78. How to get driving net of an instance‏‎ (18:40, 12 August 2021)
  79. LineFile data from input files‏‎ (17:23, 31 August 2021)
  80. Source code customization & Stable release services‏‎ (13:28, 11 October 2021)
  81. How to get all Verilog files being analyzed‏‎ (08:57, 20 October 2021)
  82. How to traverse scope hierarchy‏‎ (14:45, 26 October 2021)
  83. Statically elaborate with different values of parameters‏‎ (12:38, 27 October 2021)
  84. How to parse a string‏‎ (21:09, 26 January 2022)
  85. Black box, empty box, and unknown box‏‎ (15:45, 4 March 2022)
  86. Preserving user nets - preventing nets from being optimized away‏‎ (11:17, 1 April 2022)
  87. How to ignore certain modules while analyzing input RTL files‏‎ (09:26, 14 April 2022)
  88. Access attributes in parsetree‏‎ (14:22, 3 May 2022)
  89. How to get packed dimensions of enum‏‎ (17:46, 11 May 2022)
  90. Simple examples of VHDL visitor pattern‏‎ (17:21, 12 May 2022)
  91. Prettyprint all modules in the design hierarchy‏‎ (12:12, 19 July 2022)
  92. How to tell if a module has encrypted contents‏‎ (19:42, 24 August 2022)
  93. Simple example of visitor pattern‏‎ (11:08, 26 August 2022)
  94. System attributes‏‎ (00:12, 11 September 2022)
  95. Python pretty-printer for gdb‏‎ (11:28, 13 September 2022)
  96. Modules with " 1", " 2", ..., suffix in their names‏‎ (14:46, 27 September 2022)
  97. Modules with ' 1' ' 2' suffix in their names‏‎ (17:57, 27 September 2022)
  98. Replacing Verific built-in primitives/operators with user implementations‏‎ (17:49, 24 October 2022)
  99. How to save computer resources‏‎ (15:12, 28 October 2022)
  100. Evaluate 'for-generate' loop‏‎ (15:32, 17 November 2022)
  101. Verilog Port Expressions‏‎ (14:40, 13 February 2023)
  102. How to ignore parameters/generics in elaboration‏‎ (11:14, 17 February 2023)
  103. Compile-time/run-time flags‏‎ (20:31, 2 March 2023)
  104. Difference between RTL and gate-level simulations - Flipflop with async set and async reset‏‎ (15:02, 14 March 2023)
  105. Parse select modules only and ignore the rest‏‎ (17:23, 5 June 2023)
  106. Escaped identifiers in RTL files and in Verific data structures‏‎ (08:51, 16 June 2023)
  107. How to use RegisterPragmaRefCallBack()‏‎ (12:34, 2 August 2023)
  108. Finding hierarchical paths of a Netlist‏‎ (13:19, 22 August 2023)
  109. Static elaboration‏‎ (14:55, 14 September 2023)
  110. Create a Netlist Database from scratch (not from RTL elaboration)‏‎ (12:20, 20 September 2023)
  111. Traverse instances in parsetree‏‎ (10:59, 29 September 2023)
  112. How to change name of id in Verilog parsetree‏‎ (14:15, 10 October 2023)
  113. How to get best support from Verific‏‎ (17:25, 11 October 2023)
  114. Modules/design units with " default" suffix in their names‏‎ (08:37, 23 October 2023)
  115. Notes on analysis‏‎ (21:53, 31 October 2023)
  116. How to get type/initial value of parameters‏‎ (17:37, 3 November 2023)
  117. Constant expression replacement‏‎ (09:51, 17 November 2023)
  118. How to use MessageCallBackHandler Class‏‎ (16:22, 5 December 2023)
  119. How to get linefile data of macros - Macro callback function‏‎ (13:14, 11 December 2023)
  120. Message handling‏‎ (12:48, 12 December 2023)
  121. Pretty-print a module and the packages imported by the module‏‎ (22:49, 14 December 2023)
  122. Create DOT diagram of parse tree‏‎ (19:08, 12 January 2024)
  123. Instance - Module binding order‏‎ (17:41, 25 January 2024)
  124. Post processing port resolution of black boxes‏‎ (17:44, 19 February 2024)
  125. Main Page‏‎ (22:25, 27 February 2024)
  126. SystemVerilog "std" package‏‎ (17:05, 28 February 2024)
  127. In Verilog parsetree adding names to unnamed instances‏‎ (19:52, 3 April 2024)

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