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1. A customer wants to analyze/elaborate
2. Access attributes of ports in parsetree
3. Bit-blasting a multi-port RAM instance
4. Black box, empty box, and unknown box
5. Comment out a line using test-based design modification and parsetree modification
6. Compile-time/run-time flags
7. Constant expression replacement
8. Create a Netlist Database from scratch (not from RTL elaboration)
9. Cross-reference between the original RTL files and the elaborated netlist
10. Defined macros become undefined - MFCU vs SFCU
11. Design with System Verilog and Verilog 2001 files
12. Design with VHDL-1993 and VHDL-2008 files
13. Does Verific build CDFG?
14. Does Verific support XMR?
15. Does Verific support cross
16. Does Verific support cross module references (XMR)?
17. Extract clock enable
18. General
19. Getting instances' parameters
20. How do I know
21. How do I know what language a Netlist in the netlist database comes from?
22. How to change name of id in Verilog parsetree
23. How to check for errors in analysis/elaboration
24. How to create a Netlist database from scratch (not from RTL input)
25. How to create new module in Verilog parsetree
26. How to find port dimensions
27. How to get all Verilog files being analyzed
28. How to get best support from Verific
29. How to get enums from Verilog parsetree
30. How to get full hierarchy ID path
31. How to get library containing nested module
32. How to get linefile information of macro definitions
33. How to get module ports from Verilog parsetree
34. How to get packed dimensions of enum
35. How to get type/initial value of parameters
36. How to identify packages being imported into a module
37. How to ignore a (not used) parameter/generic in elaboration.
38. How to ignore parameters/generics in elaboration
39. How to make lives easier
40. How to tell if a module has encrypted contents
41. How to use RegisterCallBackMsg()
42. I'm using -v, -y,
43. I have a design consisting of
44. Included files associated with a Verilog source file
45. Instance - Module binding order
46. Logic optimization across hierarchy boundaries
47. Macro Callback example
48. Main Page
49. Memory elements of a RamNet
50. Message handling

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