Difference between revisions of "System attributes"
From Verific Design Automation FAQ
(Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...") |
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Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. | Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. | ||
− | To distinguish with user-declared attributes, the key (name) of a system attribute has space as the first character. | + | To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character. |
Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute. | Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute. | ||
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(" named_group", named_group) | (" named_group", named_group) | ||
(" GATE_TYPE", "gated_clock") | (" GATE_TYPE", "gated_clock") | ||
− | (" creating_port_refs", | + | (" creating_port_refs", "1") |
(" enum_encoding", user_encoding) // DFF | (" enum_encoding", user_encoding) // DFF | ||
(" PROCESS_ID", buffer) // ReadPort/WritePort only | (" PROCESS_ID", buffer) // ReadPort/WritePort only | ||
Line 17: | Line 17: | ||
(" wired", "1") | (" wired", "1") | ||
(" is_up_dir", "1") | (" is_up_dir", "1") | ||
− | (" original_name", | + | (" original_name", name) // original name in the input file, for nets being renamed to avoid to name conflict |
− | (" supply0", | + | (" supply0", "1") // from Verilog "supply0" construct |
− | (" supply1", | + | (" supply1", "1") // from Verilog "supply1" construct |
(" specify_cond", cond_pp) // SDF only | (" specify_cond", cond_pp) // SDF only | ||
(" package_net", "1") | (" package_net", "1") | ||
− | (" global_clocking_ref", | + | (" global_clocking_ref", "1") // SVA |
− | (" sva_clock_ref", | + | (" sva_clock_ref", "1") // SVA |
(" enum_encoding", user_encoding) | (" enum_encoding", user_encoding) | ||
NetBus | NetBus | ||
− | (" original_name", | + | (" original_name", name) |
Port | Port | ||
− | (" orig_port_name", | + | (" orig_port_name", name) |
− | (" created_from_test_cell", | + | (" created_from_test_cell", "1") // created from test cell in SynLib |
(" open_port", "1") | (" open_port", "1") | ||
PortBus | PortBus | ||
− | (" orig_port_name", | + | (" orig_port_name", name) |
Netlist | Netlist | ||
− | (" language", "edif") // | + | (" language", "edif") // the language it comes from - "edif", "verilog", "vhdl", "upf", "synlib" |
(" cell_name", module_name) // original module/unit name in input file | (" cell_name", module_name) // original module/unit name in input file | ||
− | (" from_netlist_reader", "1") | + | (" from_netlist_reader", "1") // from structural netlist reader (not synthesized from RTL) |
(" primitive", "1") | (" primitive", "1") | ||
(" unknown_design", "2")) // "1" for Verilog instance, "2" for VHDL instance | (" unknown_design", "2")) // "1" for Verilog instance, "2" for VHDL instance | ||
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</nowiki> | </nowiki> | ||
− | To access attributes of a DesignObj, use | + | To access the attributes of a DesignObj, use macro FOREACH_ATTRIBUTE. For example: |
+ | |||
+ | C++: | ||
<nowiki> | <nowiki> | ||
− | + | Netlist *netlist = ....; // or any other derived class from DesignObj | |
− | + | Att *attr; | |
− | + | MapIter mi; | |
− | + | FOREACH_ATTRIBUTE(netlist, mi, attr) { | |
− | + | const char *key = (attr) ? attr->Key() : 0 ; | |
− | + | if (!key) continue ; | |
− | + | if (key[0] == ' ') continue ; // if you want to skip system attributes | |
− | + | // Do whatever you want here, e.g. | |
− | + | Message::Msg(VERIFIC_INFO, 0, 0, " -- attribute name: %s, value: %s", attr->Key(), attr->Value()); | |
− | + | } | |
</nowiki> | </nowiki> |
Revision as of 01:36, 15 June 2020
Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database.
To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character.
Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute.
Instance (" named_group", named_group) (" GATE_TYPE", "gated_clock") (" creating_port_refs", "1") (" enum_encoding", user_encoding) // DFF (" PROCESS_ID", buffer) // ReadPort/WritePort only (" is_concurrent", "1") // ReadPort/WritePort only (" BLOCKING", "1") // ReadPort/WritePort only Net (" basic_constant", const_val) // is driven by a constant and also connected to a blackbox (" wired", "1") (" is_up_dir", "1") (" original_name", name) // original name in the input file, for nets being renamed to avoid to name conflict (" supply0", "1") // from Verilog "supply0" construct (" supply1", "1") // from Verilog "supply1" construct (" specify_cond", cond_pp) // SDF only (" package_net", "1") (" global_clocking_ref", "1") // SVA (" sva_clock_ref", "1") // SVA (" enum_encoding", user_encoding) NetBus (" original_name", name) Port (" orig_port_name", name) (" created_from_test_cell", "1") // created from test cell in SynLib (" open_port", "1") PortBus (" orig_port_name", name) Netlist (" language", "edif") // the language it comes from - "edif", "verilog", "vhdl", "upf", "synlib" (" cell_name", module_name) // original module/unit name in input file (" from_netlist_reader", "1") // from structural netlist reader (not synthesized from RTL) (" primitive", "1") (" unknown_design", "2")) // "1" for Verilog instance, "2" for VHDL instance (" changed_by_interface_overwrite", "1") (" changed_by_hier_ref", "1") (" celldefine","1") (" package", "1") (" upf_uniquified", "1"))
To access the attributes of a DesignObj, use macro FOREACH_ATTRIBUTE. For example:
C++:
Netlist *netlist = ....; // or any other derived class from DesignObj Att *attr; MapIter mi; FOREACH_ATTRIBUTE(netlist, mi, attr) { const char *key = (attr) ? attr->Key() : 0 ; if (!key) continue ; if (key[0] == ' ') continue ; // if you want to skip system attributes // Do whatever you want here, e.g. Message::Msg(VERIFIC_INFO, 0, 0, " -- attribute name: %s, value: %s", attr->Key(), attr->Value()); }