Using stream input to ignore input file

This example shows how to use stream input to ignore input files that meet certain conditions.

The example uses only filename as the "ignore" category. But you can have other tests.

C++:

#include "VerificStream.h"
#include "veri_file.h"
#include "Strings.h"
#include "Message.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific;
#endif

// Define a stream class that always returns EOF when read.
class my_eof_stream : public verific_stream
{
public:
    my_eof_stream() : verific_stream() { }
    virtual ~my_eof_stream() { }

    virtual bool read(char *buf, long max_size) { *buf = '\0'; (void) max_size; return true; }
    virtual std::streamsize gcount() const      { return 0; }
    virtual bool            eof() const         { return 1; }
    virtual bool            fail() const        { return 0; }
    virtual bool            bad() const         { return 0; }
};

static verific_stream *
my_file_stream(const char *file_name)
{
    if (Strings::compare("ToBeIgnored.v", file_name)) { // Use your own condition here
        Message::Msg(VERIFIC_INFO, 0, 0, "Ignoring file %s", file_name);
        return new my_eof_stream(); // Return the EOF stream object (file is not used)
    }
    return 0;
}

int main(int argc, const char **argv)
{
    Message::PrintLine("Normal read, will produce error.");
    veri_file::Analyze("test.v", veri_file::VERILOG_2K);

    Message::PrintLine("");
    Message::PrintLine("Reset parsetree and read again, ignoring the \"bad\" file.");

    // Reset parser
    veri_file::ResetParser();
    // Ignore the included file this time
    veri_file::RegisterFlexStreamCallBack(my_file_stream);

    // Should not error out
    if (!veri_file::Analyze("test.v", veri_file::VERILOG_2K)) return 1;
    veri_file::PrettyPrint("pp_out.v", 0);

    return 0;
}
 

test.v:

module test ();
`include "ToBeIgnored.v"
endmodule
 

ToBeIgnored.v:

This file is not Verilog-legal.
It will be ignored.
 

Run:

$ test-linux 
-- Normal read, will produce error.
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(2): INFO: analyzing included file 'ToBeIgnored.v' (VERI-1328)
ToBeIgnored.v(1): ERROR: syntax error near 'is' (VERI-1137)
test.v(2): INFO: back to file 'test.v' (VERI-2320)
-- Verilog file 'test.v' ignored due to errors (VERI-1483)
-- 
-- Reset parsetree and read again, ignoring the "bad" file.
-- Analyzing Verilog file 'test.v' (VERI-1482)
INFO: Ignoring file ToBeIgnored.v
test.v(2): INFO: analyzing included file 'ToBeIgnored.v' (VERI-1328)
test.v(2): INFO: back to file 'test.v' (VERI-2320)
-- Pretty printing all design elements in all libraries to file 'pp_out.v' (VERI-1492)
$ 
 

pp_out.v:

module test () ;
endmodule