Verilog/C++: How to use IsUserDeclared() : Example for port associations

Verific objects that are derived from DesignObj can be checked for Linefile information using IsUserDeclared(). If the derived object, such as a port, instance, or netlist contains Linefile information, IsUserDeclared() will return 1, otherwise it will return 0. Linefile information is stored for all objects read from HDL source files, so IsUserDeclared() can be used to check whether an instance was created as a result of the HDL input, versus being an operator or primitive that was created by Verific.

When a design has already passed RTL elaboration, any objects that are added to it are, by default, NOT user-declared. In situations where it may be necessary to make these objects user-declared, simply providing Linefile information for the object will do the job. One example where this may be desired is when we write out a Verilog netlist after making design modifications. Any object added without Linefile data will not be considered user-declared, and because Verific writes non-user-declared instances using implicit port-ordering syntax, thsee objects will be written out as such. However Verific writes out the other design objects that were derived from HDL using explicit named-association syntax. By adding Linefile information to these new objects added after RTL elaboration, the resulting netlist will have a consistent naming convention for all instantiations.

One way to add Linefile() information to an object is during its creation. Adding to a new netlist can be done as follows :

       Netlist *newNetlist2 = newCell2->Add(new Netlist("mymod2", top->Linefile())) ;

and adding to a port :

       newNetlist2->Add(new Port("out", DIR_OUT, top->Linefile())) ;

Please see below for a complete example on how IsUserDeclared() is used.