Difference between revisions of "Verilog/C++: How to use IsUserDeclared() and port associations"

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C++
 
C++
 
+
//
 
#include <iostream>
 
#include <iostream>
 
#include "Map.h"        // Make associated hash table class Map available
 
#include "Map.h"        // Make associated hash table class Map available

Revision as of 16:02, 13 May 2020

Verific objects that are derived from DesignObj can be checked for Linefile information using IsUserDeclared(). If the derived object, such as a port, instance, or netlist contains Linefile information, IsUserDeclared() will return 1, otherwise it will return 0. Linefile information is stored for all objects read from HDL source files, so IsUserDeclared() can be used to check whether an instance was created as a result of the HDL input, versus being an operator or primitive that was created by Verific.

When a design has already passed RTL elaboration, any objects that are added to it are, by default, NOT user-declared. In situations where it may be necessary to make these objects user-declared, simply providing Linefile information for the object will do the job. One example where this may be desired is when we write out a Verilog netlist after making design modifications. Any object added without Linefile data will not be considered user-declared, and because Verific writes non-user-declared instances using implicit port-ordering syntax, thsee objects will be written out as such. However Verific writes out the other design objects that were derived from HDL using explicit named-association syntax. By adding Linefile information to these new objects added after RTL elaboration, the resulting netlist will have a consistent naming convention for all instantiations.

One way to add Linefile() information to an object is during its creation. Adding to a new netlist can be done as follows :

       Netlist *newNetlist2 = newCell2->Add(new Netlist("mymod2", top->Linefile())) ;

and adding to a port :

       newNetlist2->Add(new Port("out", DIR_OUT, top->Linefile())) ;

Please see below for a complete example on how IsUserDeclared() is used.

C++ //

  1. include <iostream>
  2. include "Map.h" // Make associated hash table class Map available
  3. include "Message.h" // Make message handlers available
  4. include "veri_file.h" // Make verilog reader available
  5. include "VeriWrite.h" // Make verilog writer available
  6. include "DataBase.h" // Make (hierarchical netlist) database API available
  7. include "Strings.h" // Definition of class to manipulate copy, concatenate, create etc...
  1. ifdef VERIFIC_NAMESPACE

using namespace Verific ;

  1. endif

int main(int argc, char **argv) {

   // Analyze and elaborate the design
   if (!veri_file::Read("top.v","work", veri_file::VERILOG_2K /*v2k*/)) return 1 ;
   // Get a handle to the top-level netlist
   Netlist *top = Netlist::PresentDesign() ;
   if (!top) {
       Message::PrintLine("Cannot find any handle to the top-level netlist") ;
       return 3 ;
   }
   // Print name of the top level module
   Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is %s(%s)",
                top->Owner()->Name(), top->Name()) ;
   // Add two more ports to the top level module
   // Port "c" is added without Linefile info, port "d" has Linefile borrowed from module "top"
   Port *port_c, *port_d ;
   port_c = top->Add(new Port("c", DIR_OUT)) ;
   port_d = top->Add(new Port("d", DIR_OUT, top->Linefile())) ;
   // Add two nets to connect to the two ports "c" and "d"
   Net *net_c = top->Add(new Net("c")) ;
   if (net_c && port_c)
       net_c->Connect(port_c) ;
   Net *net_d = top->Add(new Net("d")) ;
   if (net_d && port_d)
       net_d->Connect(port_d) ;