Verilog ports being renamed

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Q: Why are the ports in original Verilog file renamed to p1, p2, ....?

Input file:

   module foo ( datain[0],  datain[0] /* same net into multiple port expression */,
                datain[2:1]  /* part-select  port expression */,
                /* empty port expression */,
                {datain[2],datain[1], datain[1]} /* concatenation in port expression */
               ) ;
       input [2:0] datain ;
       ...
   endmodule

Output netlist:

   module foo (p1, p2, p3, , p7);   // test.v(1[8:11])
       input p1;   // test.v(6[17:23])
       input p2;   // test.v(6[17:23])
       input [1:0]p3;
       input [2:0]p7;
       ...     
   endmodule


The items in the () after the module name are not "port names," rather, they are "port expressions." Verilog defines that the port expressions on this module CANNOT be accessed by name (only by order). This means you cannot rely on the port names to be one thing or another.

Verific chose to not adjust to any particular naming scheme for complex port expressions, which also allows us to error out if named port instantiation occurs where the language disallows it.

The original port expression of the renamed port is saved as attributes " orig_port_name" attached to the port.

   key: " orig_port_name", value: port expression

For the testcase above:

   input p1 /* verific  orig_port_name=datain[0] */ ;
   input p2 /* verific  orig_port_name=datain[0] */ ;
   input [1:0]p3 /* verific  orig_port_name=datain[2] datain[1] */ ;
   input [2:0]p7 /* verific  orig_port_name=datain[2] datain[1] datain[1] */ ;