Revision history of "Verilog ports being renamed"

Jump to: navigation, search

Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.

  • (cur | prev) 14:58, 22 July 2016Hoa (Talk | contribs). . (1,602 bytes) (+1,602). . (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] same net into multiple port expression: ,...")