Difference between revisions of "Instance - Module binding order"
From Verific Design Automation FAQ
(Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind...") |
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# While parsing: | # While parsing: | ||
## `uselib | ## `uselib | ||
| − | |||
## -L | ## -L | ||
| + | ## -work | ||
## -y/-v | ## -y/-v | ||
# While elaborating: | # While elaborating: | ||
## configurations | ## configurations | ||
## already resolved module from analysis, ie, order of parsing (above) | ## already resolved module from analysis, ie, order of parsing (above) | ||
Revision as of 15:27, 7 October 2022
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- `uselib
- -L
- -work
- -y/-v
- While elaborating:
- configurations
- already resolved module from analysis, ie, order of parsing (above)
