User contributions
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- 10:23, 8 May 2024 (diff | hist) . . (+186) . . Source code customization & Stable release services (current)
- 11:35, 23 April 2024 (diff | hist) . . (+3,785) . . N Using TypeRange table to retrieve the originating type-range for an id (Created page with "C++: <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Map.h" #include "Set.h" #ifdef VERIFIC_NAMESPACE using namespace Verific ; #endif int main() { Runt...") (current)
- 11:30, 23 April 2024 (diff | hist) . . (+190) . . Main Page (current)
- 19:52, 3 April 2024 (diff | hist) . . (+52) . . In Verilog parsetree adding names to unnamed instances (current)
- 17:05, 28 February 2024 (diff | hist) . . (+114) . . SystemVerilog "std" package (current)
- 17:41, 25 January 2024 (diff | hist) . . (-6) . . Instance - Module binding order (current)
- 09:51, 17 November 2023 (diff | hist) . . (-1) . . Constant expression replacement (current)
- 21:53, 31 October 2023 (diff | hist) . . (-5) . . Notes on analysis (current)
- 21:52, 31 October 2023 (diff | hist) . . (+136) . . Notes on analysis
- 12:13, 20 October 2023 (diff | hist) . . (0) . . Notes on analysis
- 09:32, 20 October 2023 (diff | hist) . . (+126) . . Notes on analysis
- 17:25, 11 October 2023 (diff | hist) . . (+268) . . How to get best support from Verific (current)
- 14:15, 10 October 2023 (diff | hist) . . (-8) . . How to change name of id in Verilog parsetree (current)
- 10:59, 29 September 2023 (diff | hist) . . (-86) . . Traverse instances in parsetree (current)
- 10:57, 29 September 2023 (diff | hist) . . (+367) . . Traverse instances in parsetree
- 13:19, 22 August 2023 (diff | hist) . . (+3,244) . . N Finding hierarchical paths of a Netlist (Created page with "This application displays all hierarchical paths of Netlist of Cell 'bot1' in the Netlist Database. <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Strings.h...") (current)
- 13:12, 22 August 2023 (diff | hist) . . (+102) . . Main Page
- 14:49, 8 August 2023 (diff | hist) . . (-2) . . Static elaboration
- 14:49, 8 August 2023 (diff | hist) . . (+43) . . Static elaboration
- 14:48, 8 August 2023 (diff | hist) . . (+31) . . Static elaboration
- 12:34, 2 August 2023 (diff | hist) . . (+1,679) . . N How to use RegisterPragmaRefCallBack() (Created page with "Here is a small example showing how to use RegisterPragmaRefCallBack(): <nowiki> #include <iostream> #include "veri_file.h" #include "vhdl_file.h" #include "Message.h" usin...") (current)
- 12:25, 2 August 2023 (diff | hist) . . (+96) . . Main Page
- 08:40, 26 July 2023 (diff | hist) . . (+57) . . How to get linefile data of macros - Macro callback function
- 08:51, 16 June 2023 (diff | hist) . . (+90) . . Escaped identifiers in RTL files and in Verific data structures (current)
- 17:23, 5 June 2023 (diff | hist) . . (+1,333) . . Parse select modules only and ignore the rest (current)
- 13:58, 24 April 2023 (diff | hist) . . (+3,728) . . N In Verilog parsetree adding names to unnamed instances (Created page with "In Verilog, each module instantiation should have a name. But name is optional for UDP instantiation and Verilog primitive instantiation. Verific issues a warning for unnamed...")
- 13:50, 24 April 2023 (diff | hist) . . (+1) . . Main Page
- 13:50, 24 April 2023 (diff | hist) . . (+130) . . Main Page
- 15:02, 14 March 2023 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset (current)
- 14:59, 14 March 2023 (diff | hist) . . (0) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 11:23, 24 February 2023 (diff | hist) . . (-34) . . Notes on analysis
- 11:26, 21 February 2023 (diff | hist) . . (+26) . . Instance - Module binding order
- 14:40, 13 February 2023 (diff | hist) . . (+3,195) . . Verilog Port Expressions (current)
- 10:59, 10 February 2023 (diff | hist) . . (+1,742) . . Verilog Port Expressions
- 10:30, 10 February 2023 (diff | hist) . . (-51) . . Main Page
- 10:27, 10 February 2023 (diff | hist) . . (0) . . m Verilog Port Expressions (Hoa moved page Verilog ports being renamed to Verilog Port Expressions)
- 10:27, 10 February 2023 (diff | hist) . . (+38) . . N Verilog ports being renamed (Hoa moved page Verilog ports being renamed to Verilog Port Expressions) (current)
- 15:59, 25 January 2023 (diff | hist) . . (+296) . . How to get best support from Verific
- 10:35, 15 December 2022 (diff | hist) . . (+116) . . Static elaboration
- 15:32, 17 November 2022 (diff | hist) . . (+6,695) . . N Evaluate 'for-generate' loop (Created page with "C++ application: <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriBaseValue_Stat.h" #include "VeriVisitor.h" #include "VeriExpression.h" #include "VeriC...") (current)
- 15:28, 17 November 2022 (diff | hist) . . (+79) . . Main Page
- 15:12, 28 October 2022 (diff | hist) . . (+279) . . How to save computer resources (current)
- 17:49, 24 October 2022 (diff | hist) . . (-1) . . Replacing Verific built-in primitives/operators with user implementations (current)
- 16:27, 7 October 2022 (diff | hist) . . (0) . . Instance - Module binding order
- 17:57, 27 September 2022 (diff | hist) . . (+8) . . Modules with ' 1' ' 2' suffix in their names (current)
- 15:12, 27 September 2022 (diff | hist) . . (+2,091) . . N Modules with ' 1' ' 2' suffix in their names (Created page with "Static elaboration process adds the suffix "_<number>" to the module name when: #Module contains hierarchical identifier(s), and #Hierarchical identifier(s) in that module poi...")
- 15:11, 27 September 2022 (diff | hist) . . (-7) . . Main Page
- 14:46, 27 September 2022 (diff | hist) . . (+7) . . Modules with " 1", " 2", ..., suffix in their names (current)
- 14:45, 27 September 2022 (diff | hist) . . (+22) . . Modules with " 1", " 2", ..., suffix in their names
- 14:44, 27 September 2022 (diff | hist) . . (-34) . . Modules with " 1", " 2", ..., suffix in their names
- 14:42, 27 September 2022 (diff | hist) . . (+676) . . Modules with " 1", " 2", ..., suffix in their names
- 13:54, 27 September 2022 (diff | hist) . . (-3) . . Modules with " 1", " 2", ..., suffix in their names
- 13:53, 27 September 2022 (diff | hist) . . (+44) . . Modules with " 1", " 2", ..., suffix in their names
- 13:52, 27 September 2022 (diff | hist) . . (+1,379) . . N Modules with " 1", " 2", ..., suffix in their names (Created page with "**** Under construction **** Static elaboration process adds the "_<number>" to the module name when: 1) Module contains hierarchical identifier(s), and 2) Hierarchical ident...")
- 13:48, 27 September 2022 (diff | hist) . . (-1) . . Main Page
- 13:47, 27 September 2022 (diff | hist) . . (+163) . . Main Page
- 00:12, 11 September 2022 (diff | hist) . . (0) . . System attributes (current)
- 00:08, 11 September 2022 (diff | hist) . . (+192) . . System attributes
- 16:45, 9 September 2022 (diff | hist) . . (+130) . . How to save computer resources
- 16:43, 9 September 2022 (diff | hist) . . (+1,133) . . How to save computer resources
- 11:08, 26 August 2022 (diff | hist) . . (+17) . . Simple example of visitor pattern (current)
- 19:42, 24 August 2022 (diff | hist) . . (-9) . . How to tell if a module has encrypted contents (current)
- 22:59, 1 August 2022 (diff | hist) . . (0) . . Compile-time/run-time flags
- 22:52, 1 August 2022 (diff | hist) . . (+52) . . Compile-time/run-time flags
- 12:12, 19 July 2022 (diff | hist) . . (+35) . . Prettyprint all modules in the design hierarchy (current)
- 11:46, 19 July 2022 (diff | hist) . . (-8) . . Main Page
- 17:21, 12 May 2022 (diff | hist) . . (-119) . . Simple examples of VHDL visitor pattern (current)
- 17:16, 12 May 2022 (diff | hist) . . (-77) . . Simple examples of VHDL visitor pattern
- 17:16, 12 May 2022 (diff | hist) . . (+2,489) . . N Simple examples of VHDL visitor pattern (Created page with " <nowiki> [hoa@awing0 220512b]$ cat test.cpp #include "vhdl_file.h" #include "VhdlUnits.h" #include "VhdlIdDef.h" #include "VhdlValue_Elab.h" #include "Strings.h" #ifdef VERI...")
- 17:14, 12 May 2022 (diff | hist) . . (+11) . . Main Page
- 17:13, 12 May 2022 (diff | hist) . . (+87) . . Main Page
- 14:22, 3 May 2022 (diff | hist) . . (+30) . . Access attributes in parsetree (current)
- 09:26, 14 April 2022 (diff | hist) . . (+3,558) . . N How to ignore certain modules while analyzing input RTL files (Created page with "The code example below shows how to ignore certain modules in the input RTL files. The ignored modules will not be present in the parsetree. C++ code: <nowiki> #include "Arr...") (current)
- 08:49, 14 April 2022 (diff | hist) . . (+145) . . Main Page
- 15:45, 4 March 2022 (diff | hist) . . (0) . . Black box, empty box, and unknown box (current)
- 15:44, 4 March 2022 (diff | hist) . . (+75) . . Black box, empty box, and unknown box
- 20:05, 10 February 2022 (diff | hist) . . (-66) . . How to save computer resources
- 21:09, 26 January 2022 (diff | hist) . . (-1) . . How to parse a string (current)
- 21:08, 26 January 2022 (diff | hist) . . (-15) . . How to parse a string
- 11:38, 26 January 2022 (diff | hist) . . (+31) . . Notes on analysis
- 12:56, 29 December 2021 (diff | hist) . . (+383) . . Static elaboration
- 21:30, 3 December 2021 (diff | hist) . . (+150) . . System attributes
- 21:26, 3 December 2021 (diff | hist) . . (+135) . . System attributes
- 18:57, 1 December 2021 (diff | hist) . . (+90) . . Black box, empty box, and unknown box
- 17:52, 3 November 2021 (diff | hist) . . (+8) . . Black box, empty box, and unknown box
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Statically elaborate with different values of parameters (current)
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Simple example of visitor pattern
- 14:45, 26 October 2021 (diff | hist) . . (+133) . . How to traverse scope hierarchy (current)
- 16:12, 20 October 2021 (diff | hist) . . (-1) . . How to parse a string
- 10:34, 15 October 2021 (diff | hist) . . (-10) . . Main Page
- 10:32, 15 October 2021 (diff | hist) . . (-54) . . How to get best support from Verific
- 09:21, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (+2) . . Notes on analysis
- 08:51, 15 October 2021 (diff | hist) . . (+152) . . Notes on analysis
- 17:49, 14 October 2021 (diff | hist) . . (+1) . . Notes on analysis
- 15:55, 12 October 2021 (diff | hist) . . (+66) . . How to save computer resources
- 11:32, 8 October 2021 (diff | hist) . . (-28) . . Main Page
- 11:31, 8 October 2021 (diff | hist) . . (+108) . . Escaped identifiers in RTL files and in Verific data structures
- 11:13, 8 October 2021 (diff | hist) . . (-33) . . System attributes
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