Difference between revisions of "Finding hierarchical paths of a Netlist"
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Latest revision as of 12:19, 22 August 2023
This application displays all hierarchical paths of Netlist of Cell 'bot1' in the Netlist Database.
#include "veri_file.h"
#include "DataBase.h"
#include "Strings.h"
#include "Array.h"
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif
static void
GetHierPaths(const Netlist *nl, const char *suffix, Array &paths)
{
if (!nl) return ;
Set *refs = nl->GetReferences() ;
char *new_suffix ;
if (!refs) {
// Reached top:
Cell *cell = nl->Owner() ;
const char *cell_name = (cell) ? cell->Name() : "" ;
new_suffix = (suffix) ? Strings::save(cell_name, ".", suffix) : Strings::save(cell_name) ;
paths.InsertLast(new_suffix) ;
return ;
}
// Get all the paths going up via these instances:
SetIter si ;
Instance *inst ;
FOREACH_SET_ITEM(refs, si, &inst) {
// Create the new suffix with this instance name:
new_suffix = (suffix) ? Strings::save(inst->Name(), ".", suffix) : Strings::save(inst->Name()) ;
GetHierPaths(inst->Owner(), new_suffix, paths) ;
Strings::free(new_suffix) ;
}
}
static void
PrintPaths(const Netlist *nl, Array &paths)
{
if (!nl || !paths.Size()) return ;
const Cell *cell = nl->Owner() ;
const char *cell_name = (cell) ? cell->Name() : "" ;
unsigned i ;
char *path ;
FOREACH_ARRAY_ITEM(&paths, i, path) {
nl->Info("Netlist %s(%s) is instantiated as '%s'", cell_name, nl->Name(), path) ;
Strings::free(path) ;
}
paths.Reset() ; // Elements are deleted above
}
int main()
{
veri_file::Read("test.v", "work", veri_file::SYSTEM_VERILOG);
// Get the netlist "bot1":
Libset *glbl = Libset::Global() ;
Library *lib = glbl->GetLibrary("work") ;
Cell *cell = (lib) ? lib->GetCell("bot1") : 0 ;
Netlist *nl = (cell) ? cell->GetFirstNetlist() : 0 ;
// Get all the hierarchical paths of this netlist:
Array paths ;
GetHierPaths(nl, 0 /* no suffix */, paths) ;
// Print all those paths:
PrintPaths(nl, paths) ;
return 0 ;
}
RTL testcase::
module top1();
wire in_top1;
mid1 m11();
mid1 m12();
mid2 m21();
bot1 b11();
endmodule
module top2();
wire in_top2;
bot1 b12();
endmodule
module mid1();
wire in_mid1;
bot1 b1();
bot2 b2();
endmodule
module mid2();
wire in_mid2;
bot1 b1();
endmodule
module bot1();
wire in_bot1;
endmodule
module bot2();
wire in_bot2;
endmodule
Run:
$ test-linux -- Analyzing Verilog file 'test.v' (VERI-1482) test.v(1): INFO: compiling module 'top1' (VERI-1018) test.v(14): INFO: compiling module 'mid1' (VERI-1018) test.v(25): INFO: compiling module 'bot1' (VERI-1018) test.v(29): INFO: compiling module 'bot2' (VERI-1018) test.v(20): INFO: compiling module 'mid2' (VERI-1018) test.v(9): INFO: compiling module 'top2' (VERI-1018) test.v(25): INFO: Netlist bot1() is instantiated as 'top1.m11.b1' test.v(25): INFO: Netlist bot1() is instantiated as 'top1.m12.b1' test.v(25): INFO: Netlist bot1() is instantiated as 'top1.m21.b1' test.v(25): INFO: Netlist bot1() is instantiated as 'top1.b11' test.v(25): INFO: Netlist bot1() is instantiated as 'top2.b12' $