Difference between revisions of "Does Verific support XMR?"
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'''Q: Does Verific support cross module references (XMR)?''' | '''Q: Does Verific support cross module references (XMR)?''' | ||
| − | + | With and without "hierarchy tree" feature, Verific fully supports XMR in analysis and static elaboration. But without it, support for XMR in RTL elaboration is limited. | |
| − | + | "hierarchy tree" is included in "static elaboration" feature. | |
| − | The | + | The reason for limited support in RTL elaboration (without "hierarchy tree" feature) for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported: |
module sub2(out); | module sub2(out); | ||
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sub2 i2(); | sub2 i2(); | ||
endmodule | endmodule | ||
| − | |||
Note that for XMR support in RTL elaboration (even though limited), these runtime flags need to be enabled (set to 1) before design analysis: | Note that for XMR support in RTL elaboration (even though limited), these runtime flags need to be enabled (set to 1) before design analysis: | ||
| − | |||
db_preserve_user_nets | db_preserve_user_nets | ||
db_allow_external_nets | db_allow_external_nets | ||
| + | A side effect: defparam containing interface instance reference (SystemVerilog) is not supported in RTL elaboration. | ||
| − | + | Reference: [http://www.verific.com/docs/index.php?title=Hierarchy_Tree Hierarchy Tree] | |
Revision as of 12:06, 26 March 2020
Q: Does Verific support cross module references (XMR)?
With and without "hierarchy tree" feature, Verific fully supports XMR in analysis and static elaboration. But without it, support for XMR in RTL elaboration is limited.
"hierarchy tree" is included in "static elaboration" feature.
The reason for limited support in RTL elaboration (without "hierarchy tree" feature) for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported:
module sub2(out);
output out;
assign top.i1.out = 0;
endmodule
module sub1(out);
output out;
assign top.i2.out = 0;
endmodule
module top();
sub1 i1();
sub2 i2();
endmodule
Note that for XMR support in RTL elaboration (even though limited), these runtime flags need to be enabled (set to 1) before design analysis:
db_preserve_user_nets db_allow_external_nets
A side effect: defparam containing interface instance reference (SystemVerilog) is not supported in RTL elaboration.
Reference: Hierarchy Tree
