How to save computer resources
There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime. Below are some common ones.
- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h
Highly recommended.
Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h
Highly recommended.
Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated, and the overhead of a hash table is also saved.
- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.
However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.
To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.
- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h
If you don't need the starting and ending locations including column info, turn this flag off.
For more details, see LineFile data from input files
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"
Adds directory caching for include directories with simple files (files without a directory specification).
We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.
The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
- Runtime flag "veri_ignore_always_constructs"
This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.
The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.
Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
- Runtime flag "edif_link_case_insensitive"
For EDIF input.
EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.
- Runtime flag "edif_keep_existing_view"
For EDIF input.
When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.
Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.
