How to save computer resources

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There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime. Below are some common ones.


Highly recommended.

Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.


Highly recommended.

Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated, and the overhead of a hash table is also saved.


Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.

However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.

To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.


If you don't need the starting and ending locations including column info, turn this flag off.

For more details, see LineFile data from input files

- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"

Adds directory caching for include directories with simple files (files without a directory specification).

We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.

- Runtime flag "veri_ignore_always_constructs"

This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.

The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.

Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.