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- 21:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 21:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 21:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 17:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 17:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 17:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 19:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 19:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 14:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 14:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 12:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 12:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 10:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 09:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 09:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 22:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 22:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 22:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 22:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 22:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 17:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 17:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 17:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 16:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 16:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 12:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 12:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 12:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 22:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 15:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 15:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 14:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 14:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 14:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 13:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 11:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 11:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 11:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
- 14:25, 24 August 2020 (diff | hist) . . (+5,984) . . N Fanout cone and grouping (Created page with "C++ code: <nowiki> →This application example collects instances in the fanout cone of a signal, and groups those instances into a new netlist: #include "Set.h" #include...")
- 14:20, 24 August 2020 (diff | hist) . . (+105) . . Main Page
- 09:39, 6 August 2020 (diff | hist) . . (+1,269) . . How to change name of id in Verilog parsetree
- 16:27, 30 July 2020 (diff | hist) . . (+800) . . Black box, empty box, and unknown box
- 16:06, 22 July 2020 (diff | hist) . . (+1,585) . . Included files associated with a Verilog source file (current)
- 15:44, 22 July 2020 (diff | hist) . . (+6) . . Included files associated with a Verilog source file
- 13:49, 20 July 2020 (diff | hist) . . (+2,448) . . N How to parse a string (Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct...")
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