Hierarchy tree RTL elaboration

Reference: Does Verific support XMR?

Synthesizing designs with cross-module referencing needs Hierarchy Tree feature. Below is a simple example.

Perl script:

#!/usr/bin/perl

use strict ;
use warnings ;
push (@INC,"../pm");
require "Verific.pm";

# Runtime flags to support cross-module referencing
Verific::RuntimeFlags::SetVar("db_preserve_user_nets", 1);
Verific::RuntimeFlags::SetVar("db_allow_external_nets", 1);

# hier_tree::Elaborate() expects two arrays as input
my $topmodules = new Verific::Array();
my $topunits = new Verific::Array();

# If design has Verilog source files
my $verilogfiles = new Verific::Array();
$verilogfiles->InsertLast(Verific::char_to_void("test.v"));
Verific::veri_file::AnalyzeMultipleFiles($verilogfiles);
$topmodules = Verific::veri_file::GetTopModules("work");

# If design has VHDL source files
Verific::vhdl_file::SetDefaultLibraryPath("../vdbs");
Verific::vhdl_file::Analyze("test.vhd");
$topunits = Verific::vhdl_file::GetTopDesignUnits("work");

# $netlists, returned by hier_tree::Elaborate() is an Array of Netlists
my $netlists = Verific::hier_tree::Elaborate($topmodules, $topunits);
my $netlist_array_iter = new Verific::NetlistArrayIter($netlists);
my $first = 1;
for (my $netlist = $netlist_array_iter->First();
     $netlist_array_iter->GetIndex() < $netlist_array_iter->Size();
     $netlist = $netlist_array_iter->Next()) {
    if (!defined($netlist)) {
        next;
    }
    if ($first == 1) {
        print ("Returned by hier_tree::Elaborate(): ", $netlist->Owner()->Name(), "\n");
        $first = 0;
    } else {
        print ("                                    ", $netlist->Owner()->Name(), "\n");
    }
}

my $libset = Verific::Libset::Global();
if (!defined($libset)) {
    print "ERROR: can't find global libset\n";
    exit;
}
my $lib = $libset->GetLibrary("work");
if (!defined($lib)) {
    print "ERROR: can't find library 'work'\n";
    exit;
}
my $cell = $lib->GetCell("top");
if (!defined($cell)) {
    print "ERROR: can't find cell 'top'\n";
    exit;
}
my $topnetlist = $cell->GetFirstNetlist();
if (!defined($cell)) {
    print "ERROR: can't find netlist of cell 'top'\n";
    exit;
}

# Write out netlist for module "top"
my $veriWriter = Verific::VeriWrite->new();
$veriWriter->WriteFile(sprintf("%s\_netlist.v", $topnetlist->Owner->Name()), $topnetlist) ;

exit;
 

Verilog RTL file:

module top (input [3:0] in, output [3:0] o1, o2, output [4:0]o3, o4, input [4:0] in2) ; // top-level module

    \child(arch) I(o1, o2, in);
    child #(4) I2(o3, o4, in2);

    test #(3) I3() ;
    test #(2) I4() ;
    foo I5() ;
    sub1 xi1();
    sub2 xi2();
endmodule

module test ;
parameter p = 10 ;
wire [3:0] o1, o2 ;
wire [4:0] o3, o4 ;
reg [3:0] in ;
reg [4:0] in2 ;

    child #(3) I(o1, o2, in);
    child #(4) I2(o3, o4, in2);
endmodule

module xor_gate (CompIn1, CompIn2, CompOut); // Instantiated in 'comp' entity in  Vhdl file test.vhd
     parameter p = 10 ;
     input [3:0]CompIn1;
     input [3:0]CompIn2;
     output CompOut;
endmodule

// modules with "circular XMR"
module sub2(out);
    output out;
    assign top.xi1.out = 0;
endmodule

module sub1(out);
    output out;
    assign top.xi2.out = 0;
endmodule
 

VHDL RTL file:

entity comp is -- top-level unit

   port(X, Y: in BIT_VECTOR(3 DOWNTO 0);
        Sum, Carry: out BIT);

end;

architecture Structure of comp is

    component xor_gate is
        generic (p : integer) ;
        port (CompIn1, CompIn2: in BIT_VECTOR(3 DOWNTO 0);
              CompOut : out BIT);
    end component;

-- xor_gate is a Verilog module with port names not as CompIn1, CompIn2 and CompOut.

    --for L1: xor_gate use entity WORK.xor_gate
            --port map (CompIn1, CompIn2, OPEN);

begin

   L1: xor_gate generic map (4)
       --port map (X, Y, Sum);
       port map (CompIn1 => X, CompIn2 => Y, CompOut => Sum);

end;


entity child is -- instantiated in test module in Verilog design
   generic (p : integer := 3);
   port (S1, S2: out bit_vector (p downto 0);
         I1 : in bit_vector (p downto 0));
end ;

architecture arch of child is
begin
    S1 <= I1 ;
    S2 <= not I1 ;
end ;

architecture arch1 of child is
begin
    S1 <= I1 ;
    S2 <= not I1 ;
end ;