Constant expression replacement
Q: Does Verific replace constant expressions with their respective values?
I have in my Verilog code:
parameter size = 8; reg [size-1:0] foo;
I expect the range of "foo" to be [7:0]. How do I get the range [7:0]?
If run-time flag "veri_replace_const_exprs" is set, during static elaboration, Verific will replace the following constant expressions with their respective values:
- Bounds of packed and unpacked ranges in all data declarations.
- Default values of all declared objects if those are constant.
- Delay values.
- Reject and error limits of VeriPathPulse values.
- Indexed expressions only if the indexed expression is a bit-select on the LHS of a continuous assignment or output/inout port of module or gate instantiation.
Above specific replacements are not done on un-elaborated modules because the parameter values they depend on might be changed later by other applications.
RuntimeFlags::SetVar(" veri_replace_const_exprs", 1) ;
set_runtime_flag "veri_replace_const_exprs" 1