Getting instances' parameters

C++:

#include "Map.h"
#include "Array.h"

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriExpression.h"
#include "VeriId.h"
#include "VeriScope.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, char **argv)
{
    const char *file = (argc > 1) ? argv[1] : "test.v" ;
    if (!veri_file::Analyze(file, veri_file::SYSTEM_VERILOG)) return 1 ;

    VeriModule * module = veri_file::GetModule("top");

    // Get the scope of the module:
    VeriScope *scope = module->GetScope() ;
    // Find all the declared ids in this scope:
    Map *ids = scope ? scope->DeclArea() : 0 ;
    MapIter mi ;
    VeriIdDef *id ;
    FOREACH_MAP_ITEM(ids, mi, 0, &id) { // Traverse declared ids
        if (!id || !id->IsInst()) continue ; // Consider only the instance ids
        VeriModuleInstantiation *mod_inst = id->GetModuleInstance() ;
        VeriModule *mod = mod_inst ? mod_inst->GetInstantiatedModule() : 0 ;
        if (mod) { // This is verilog module instantiation
            Message::PrintLine("Processing instance ", id->Name());
            Array *paramvalues = mod_inst->GetParamValues();
            if (paramvalues) {
                VeriExpression *assoc ;
                unsigned i ;
                FOREACH_ARRAY_ITEM(paramvalues, i, assoc) {
                    Message::PrintLine("   association string: ", assoc->GetPrettyPrintedString());
                    if (assoc->NamedFormal()) {
                        Message::PrintLine("      formal: ", assoc->NamedFormal());
                    }
                    if (assoc && assoc->IsOpen()) continue ;
                    if (assoc->GetConnection()) {
                        Message::PrintLine("      actual: ", assoc->GetConnection()->GetPrettyPrintedString());
                    }
                }
            }
        }
    }

    return 0 ;
}
 

test.v

module top ();
  wire [3:0] a0, b0;
  wire [1:0] a1, b1;
  wire [3:0] a2, b2;
  wire [7:0] a3, b3;
  FF inst0 (.A(a0), .B(b0));
  FF #(.p(2)) inst1 (.A(a1), .B(b1));
  FF #(.p(4)) inst2 (.A(a2), .B(b2));
  FF #(7) inst3 (.A(a3), .B(b3));
endmodule

module FF (A, B);
  parameter p = 4;
  input [p-1:0] A;
  output [p-1:0] B;
  assign B = A;
endmodule
 

Run output:

 
-- Analyzing Verilog file 'test.v' (VERI-1482)
-- Processing instance inst0
-- Processing instance inst1
--    association string: .p(2)
--       formal: p
--       actual: 2
-- Processing instance inst2
--    association string: .p(4)
--       formal: p
--       actual: 4
-- Processing instance inst3
--    association string: 7
--       actual: 7