Difference between revisions of "How to get module ports from Verilog parsetree"
From Verific Design Automation FAQ
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* VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module. | * VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module. | ||
| + | * VeriIdDef::IsInput()/IsOutput()/IsInout() to get the port direction | ||
| + | * VeriIdDef::GetDimensions() to check if it's an array of ports (returning 0 for a single port) | ||
* VeriIdDef::IsInterfacePort() to check if it is an interface port. | * VeriIdDef::IsInterfacePort() to check if it is an interface port. | ||
* VeriDataType::GetEnums(). If it returns non-NULL, the data type is enum. | * VeriDataType::GetEnums(). If it returns non-NULL, the data type is enum. | ||
* VeriDataType::IsTypeRef() returns 1 for user defined data types. | * VeriDataType::IsTypeRef() returns 1 for user defined data types. | ||
Revision as of 14:26, 22 July 2016
From the Verilog parsetree, how can I get the ports of a module?
You can use the following APIs:
- VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module.
- VeriIdDef::IsInput()/IsOutput()/IsInout() to get the port direction
- VeriIdDef::GetDimensions() to check if it's an array of ports (returning 0 for a single port)
- VeriIdDef::IsInterfacePort() to check if it is an interface port.
- VeriDataType::GetEnums(). If it returns non-NULL, the data type is enum.
- VeriDataType::IsTypeRef() returns 1 for user defined data types.
