How to get type/initial value of parameters
From Verific Design Automation FAQ
Q: How do I get type and initial value of parameters?
Example C++ code:
#include "veri_file.h" #include "VeriId.h" #include "VeriExpression.h" #include "Netlist.h" #include "VeriModule.h" #include <iostream> using namespace Verific ; int main() { const char *file_name = "test.v"; if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) { std::cout << "unable to analyze file " << file_name << " and mode SYSTEM_VERILOG\n"; return 1 ; } const char *top_module_name = "top"; VeriModule *top = veri_file::GetModule(top_module_name); if (!top) { std::cout <<"module " << top_module_name << " not found\n"; return 1; } Array *param_array = top->GetParameters() ; if (!param_array) { std::cout << "*** no parameters found ***\n"; return 1; } unsigned i ; VeriIdDef *param_id ; FOREACH_ARRAY_ITEM(param_array, i, param_id) { if (!param_id) continue; std::cout << "*** param name: " << param_id->Name() << " ***\n"; VeriDataType *type = param_id->GetDataType(); if (type) { std::cout << "*** type: " << type->GetPrettyPrintedString() << "***\n"; } else { std::cout << "*** type not declared ***\n"; } VeriExpression *init_value = param_id->GetInitialValue(); if (init_value) { std::cout << "*** initial value: " << init_value->GetPrettyPrintedString() << " ***\n"; } } return 0 ; }
Example Perl code:
#!/usr/bin/perl push(@INC,"../../../perlmain/install"); require "Verific.pm"; my $filename = "test.v"; my $mode = 4; # SystemVerilog - Verilog 2K: my $mode = 1; if (!Verific::veri_file::Analyze($filename, $mode)) { die "unable to analyze file $filename and mode $mode\n"; } $top_module_name = "top"; # $top is VeriModule * my $top = Verific::veri_file::GetModule($top_module_name); if (!defined($top)) { die "module $top_mod not found\n"; } my $param_array = $top->GetParameters(); if (!defined($param_array)) { print "*** no parameters found ***\n"; exit; } # now let's get an Array iterator instead of using the FOREACH_ARRAY_ITEM macro my $param_array_iter = $param_array->Iterator("VeriIdDef"); for (my $param_id = $param_array_iter->First(); $param_array_iter < $param_array_iter->Size(); $param_id = $param_array_iter->Next()) { # null check param_id.. if (!defined($param_id)) { next; } # print param name printf "* param name: %s ***\n", $param_id->Name(); # print param type # $type, if specified, is VeriDataType * my $type = $param_id->GetDataType(); if (defined($type)) { my $to_string = ""; $type->PrettyPrint(\$to_string, 0); print "*** type: $to_string ***\n"; } else { print "*** type not declared ***\n"; } # $init_value is VeriExpression * my $init_value = $param_id->GetInitialValue(); if (defined($init_value)) { my $to_string = ""; $init_value->PrettyPrint(\$to_string, 0); print "*** initial value: $to_string ***\n"; } } exit;
For example, this RTL code:
module top (a0, a1, b0, b1, c0, c1); parameter int DUMMY0 = 8; parameter logic DUMMY1 = 16; parameter WIDTH = 4; input [WIDTH-1 : 0] a0, b0, a1, b1; output [WIDTH-1 : 0] c0, c1; endmodule
Will have the following output:
-- Analyzing Verilog file 'test.v' (VERI-1482) *** param name: DUMMY0 *** *** type: int *** *** initial value: 8 *** *** param name: DUMMY1 *** *** type: logic *** *** initial value: 16 *** *** param name: WIDTH *** *** type not declared *** *** initial value: 4 ***