How to save computer resources

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- Compile flag VERIFIC_MEMORY_MANAGER

enables the new, zero-overhead, Verific memory manager, which typically reduces memory usage of the Verific software by an additional 20%.

- Compile flag DB_USE_PORT_ORDERED_PORTREF

organizes the PortRef structures in an ordered array rather than a hash table. This saves significant amount of memory, since PortRefs are no longer individually allocated, and overhead of a hash table is also saved.

- Compile flag VERILOG_QUICK_PARSE_V_FILES

Normally, -v files may contain multiple module definitions. Verilog parser is supposed to pick only the required modules from that file.

The file may not contain any of the required modules; instead it contains many other modules and is of huge size. In such case, analyzing and creating parse tree for the full file will take time and memory.

To prevent this, we provided this compile flag which will quickly parse the file and see if it is actually required or not without creating the parse tree. If it is not required we will ignore the file otherwise we will fully parse it and pick the required modules.

- Runtime flag veri_improve_include_dir_processing_runtime_for_network_file_system

Added directory caching for include directories for simple files (files without directory part).

We read the content of the directory on first encountering it while checking for an include file. The subsequent searches finds the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() call. Note that we cannot keep it alive between the two analyze calls since there can possibly be a chdir() call making the cache invalid.