Instance - Module binding order

Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?

The order of searching for modules is:

1. While parsing:
   1. `uselib
   2. -L
   3. (present working library)
   4. -y/-v (their order in an f-file is considered)
2. While elaborating:
   1. configurations
   2. already resolved module from analysis, ie, order of parsing (above)

If you would like the present working library to take precedent over other -L libraries you could add "work" at the beginning of your -L library list and set the runtime flag "veri_consider_work_as_lib_named_work_for_liblist" to 0.

Here is an example:

lib1.v:

module top;
  wire [0:0] w1;
  wire [0:1] w2;

  sub_ip1 u_sub_ip1 (.out(w2)); // should use lib2::sub_ip1
  sub_ip2 u_sub_ip2 (.out(w1)); // should use lib1::sub_ip2
endmodule
module sub_ip2 #(WIDTH = 1) (output [0:WIDTH-1] out);
  assign out = 1'b1;

  initial $display("Bound to lib1::sub_ip2 WIDTH=1");
endmodule
 

lib2.v:

module sub_ip1 #(WIDTH=2) (output [0:WIDTH-1] out);
  // Bind this to lib2::sub_ip2, WIDTH=2 by adding "work" at 
  // the beginning of -L list.
  sub_ip2 u_local_sub_ip2 (.out(out));
endmodule

module sub_ip2 #(WIDTH=2) (output [0:WIDTH-1] out);
  assign out = 2'b10;

  initial $display("Bound to lib2::sub_ip2 WIDTH=2");
endmodule
[moh@awing0 260623]$ 

 

verific.vtcl:

set_runtime_flag veri_consider_work_as_lib_named_work_for_liblist 0
analyze -work lib1 -sysv lib1.v -L lib1
analyze -work lib2 -sysv lib2.v -L lib2
elaborate -L {lib1 lib2} -module top -work lib1
write -f veri netlist_without_work.v.golden.new

cleanup -all -static 

set_runtime_flag veri_consider_work_as_lib_named_work_for_liblist 0
analyze -work lib1 -sysv lib1.v -L lib1
analyze -work lib2 -sysv lib2.v -L lib2
elaborate -L {work lib1 lib2} -module top -work lib1
write -f veri netlist_with_work.v.golden.new
[moh@awing0 260623]$ 

 

Running the script:

[moh@awing0 260623]$ /mnt/customers/Verific/VIPER_exe/viper-linux -script verific.vtcl 
-- (c) Copyright 1999 - 2026 Verific Design Automation Inc. All rights reserved
verific.vtcl(1): INFO: value of runtime flag 'veri_consider_work_as_lib_named_work_for_liblist' is 0 (CMD-2076)
-- Analyzing Verilog file 'lib1.v' (VERI-1482)
-- Analyzing Verilog file 'lib2.v' (VERI-1482)
lib1.v(1): INFO: compiling module 'top' (VERI-1018)
lib2.v(1): INFO: compiling module 'sub_ip1' (VERI-1018)
lib1.v(9): INFO: compiling module 'sub_ip2' (VERI-1018)
lib1.v(12): WARNING: system task 'display' is ignored for synthesis (VERI-1142)
lib2.v(4): WARNING: actual bit length 2 differs from formal bit length 1 for port 'out' (VERI-1330)
-- Writing netlist 'top' to Verilog file 'netlist_without_work.v.golden.new' (VDB-1030)
verific.vtcl(7): INFO: all parse trees and netlists were deleted (CMD-2055)
verific.vtcl(9): INFO: value of runtime flag 'veri_consider_work_as_lib_named_work_for_liblist' is 0 (CMD-2076)
-- Analyzing Verilog file 'lib1.v' (VERI-1482)
-- Analyzing Verilog file 'lib2.v' (VERI-1482)
lib1.v(1): INFO: compiling module 'top' (VERI-1018)
lib2.v(1): INFO: compiling module 'sub_ip1' (VERI-1018)
lib2.v(7): INFO: compiling module 'sub_ip2' (VERI-1018)
lib2.v(10): WARNING: system task 'display' is ignored for synthesis (VERI-1142)
lib1.v(9): INFO: compiling module 'sub_ip2' (VERI-1018)
lib1.v(12): WARNING: system task 'display' is ignored for synthesis (VERI-1142)
-- Writing netlist 'top' to Verilog file 'netlist_with_work.v.golden.new' (VDB-1030)
[moh@awing0 260623]$ 

 

Output with only -L libraries and no "work":

[moh@awing0 260623]$ cat netlist_without_work.v.golden.new 

//
// Verific Verilog Description of module top
//

module top ();   // lib1.v(1[8:11])
    
    
    sub_ip1 u_sub_ip1 ();   // lib1.v(5[11:31])
    sub_ip2 u_sub_ip2 ();   // lib1.v(6[11:31])
    
endmodule

//
// Verific Verilog Description of module sub_ip1
//

module sub_ip1 (out);   // lib2.v(1[8:15])
    output [0:1]out;   // lib2.v(1[47:50])
    
    
    assign out[0] = 1'b0;
    sub_ip2 u_local_sub_ip2 (.out({out[1]}));   // lib2.v(4[11:38])
    
endmodule

//
// Verific Verilog Description of module sub_ip2
//

module sub_ip2 (out);   // lib1.v(9[8:15])
    output [0:0]out;   // lib1.v(9[49:52])
    
    
    assign out[0] = 1'b1;
    
endmodule
[moh@awing0 260623]$ 

 

Output with "work" used to represent the current working library in the -L library list:

[moh@awing0 260623]$ cat netlist_with_work.v.golden.new 

//
// Verific Verilog Description of module top
//

module top ();   // lib1.v(1[8:11])
    
    
    sub_ip1 u_sub_ip1 ();   // lib1.v(5[11:31])
    sub_ip2 u_sub_ip2 ();   // lib1.v(6[11:31])
    
endmodule

//
// Verific Verilog Description of module sub_ip1
//

module sub_ip1 (out);   // lib2.v(1[8:15])
    output [0:1]out;   // lib2.v(1[47:50])
    
    
    sub_ip2_c u_local_sub_ip2 (.out({out}));   // lib2.v(4[11:38])
    
endmodule

//
// Verific Verilog Description of module sub_ip2_c
//

module sub_ip2_c (out);   // lib2.v(7[8:15])
    output [0:1]out;   // lib2.v(7[47:50])
    
    
    assign out[1] = 1'b0;
    assign out[0] = 1'b1;
    
endmodule

//
// Verific Verilog Description of module sub_ip2
//

module sub_ip2 (out);   // lib1.v(9[8:15])
    output [0:0]out;   // lib1.v(9[49:52])
    
    
    assign out[0] = 1'b1;
    
endmodule