Instance - Module binding order
From Verific Design Automation FAQ
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- While elaborating:
- already resolved module from analysis, ie, order of parsing (above)