Difference between revisions of "Instance - Module binding order"
From Verific Design Automation FAQ
| Line 5: | Line 5: | ||
# While parsing: | # While parsing: | ||
## `uselib | ## `uselib | ||
| − | |||
## -L | ## -L | ||
| + | ## (present working library) | ||
## -y/-v (their order in an f-file is considered) | ## -y/-v (their order in an f-file is considered) | ||
# While elaborating: | # While elaborating: | ||
## configurations | ## configurations | ||
## already resolved module from analysis, ie, order of parsing (above) | ## already resolved module from analysis, ie, order of parsing (above) | ||
Latest revision as of 17:41, 25 January 2024
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- `uselib
- -L
- (present working library)
- -y/-v (their order in an f-file is considered)
- While elaborating:
- configurations
- already resolved module from analysis, ie, order of parsing (above)
