Pretty-print a module and the packages imported by the module

C++:

#include <iostream>
#include <fstream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriScope.h"

#include "Map.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void print_packages_used (VeriModule *module, std::ofstream &out_stream)
{
    if (!module) return ;
    VeriScope *scope = module->GetScope() ;
    Set *using_scopes = (scope) ? scope->GetUsing() : 0 ; 
    SetIter si ;
    VeriScope *using_scope ;
    FOREACH_SET_ITEM(using_scopes, si, &using_scope) {
        VeriIdDef *mod_id2 = using_scope->GetContainingModule() ;
        VeriModule *mod2 = (mod_id2) ? mod_id2->GetModule() : 0 ; 
        print_packages_used (mod2, out_stream) ;    
        if (mod2->IsPackage()) {
            std::cout << ">>> Module '" << module->Name() << "' uses package '" << mod2->Name() << "' <<<\n";
        }   
        out_stream << "// Printing package " << mod2->Name() << endl ;
        mod2->PrettyPrint(out_stream, 0) ;
    }   
}

int main()
{
    Array files(1) ;
    // files.InsertLast("my_pack.sv") ;
    files.InsertLast("test.sv") ;
    if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) return 1 ; 

    MapIter mi ;
    VeriModule *module ;
    FOREACH_VERILOG_MODULE(mi, module){
        if (!module) continue ;

        if (module->IsPackage()) continue ; // no need to dive into package
        // if (module->IsRootModule()) continue ;

        char *outputfilename = Strings::save(module->Name(), "_pp_out.v");
        std::ofstream f(outputfilename, std::ios::out) ;
        print_packages_used (module, f) ;

        // Now  print the module:
        f << "// Printing module " << module->Name() << endl ;
        module->PrettyPrint(f, 0) ;
        f.close() ;
    }

    return 0 ;
}

 

Input Verilog:

package PKG1 ;
    typedef int my_int ;
endpackage

typedef byte my_byte ;

module test ;
    import PKG1::* ;
    my_int int1 ;
    my_byte byte1 ;
endmodule
 

Console output:

-- Analyzing Verilog file 'top.v' (VERI-1482)
>>> Module 'top' uses package 'PKG1' <<<
>>> Module 'top' uses package '$unit_top_v' <<<
 

Pretty-printed output:

// Printing package PKG1

package PKG1 ;
    typedef int my_int ;
endpackage


// Printing package $unit_test_sv

typedef byte my_byte ;


// Printing module test

module test ;
    import PKG1:: * ;
    my_int int1 ;
    my_byte byte1 ;
endmodule