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- 18:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 18:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 18:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 18:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 18:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 17:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 17:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 17:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 17:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 17:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 16:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 16:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 16:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 16:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 16:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 16:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 15:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
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