User contributions
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- 17:58, 22 October 2019 (diff | hist) . . (0) . . How to get all Verilog files being analyzed
- 14:55, 4 October 2019 (diff | hist) . . (+2,118) . . N How to ignore a (not used) parameter/generic in elaboration. (Created page with "'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?''' In RTL or static elaboration, parameterized instances are uniquified. For example, this...") (current)
- 14:37, 4 October 2019 (diff | hist) . . (+144) . . Main Page
- 14:11, 21 August 2019 (diff | hist) . . (+2,642) . . N Getting instances' parameters (Created page with "C++: <nowiki> #include "Map.h" #include "Array.h" #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriId.h" #include "VeriScope.h" #ifd...") (current)
- 14:07, 21 August 2019 (diff | hist) . . (+81) . . Main Page
- 12:21, 14 August 2019 (diff | hist) . . (-27) . . Comment out a line using test-based design modification and parsetree modification (current)
- 13:02, 30 July 2019 (diff | hist) . . (+629) . . Prettyprint all modules in the design hierarchy
- 17:10, 29 July 2019 (diff | hist) . . (-23) . . Prettyprint all modules in the design hierarchy
- 17:08, 29 July 2019 (diff | hist) . . (-1,484) . . Prettyprint all modules in the design hierarchy
- 23:29, 28 July 2019 (diff | hist) . . (-1) . . Prettyprint all modules in the design hierarchy
- 23:28, 28 July 2019 (diff | hist) . . (0) . . Prettyprint all modules in the design hierarchy
- 23:26, 28 July 2019 (diff | hist) . . (-2) . . Prettyprint all modules in the design hierarchy
- 23:25, 28 July 2019 (diff | hist) . . (-14) . . Prettyprint all modules in the design hierarchy
- 23:24, 28 July 2019 (diff | hist) . . (+12) . . Prettyprint all modules in the design hierarchy
- 23:22, 28 July 2019 (diff | hist) . . (+7,879) . . N Prettyprint all modules in the design hierarchy (Created page with "There is an API to prettyprint a module, and there is an API to prettyprint all modules in a library. But there is no single API to prettyprint all modules in the design hier...")
- 23:16, 28 July 2019 (diff | hist) . . (+117) . . Main Page
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries (current)
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries
- 16:17, 22 July 2019 (diff | hist) . . (+1,446) . . N Logic optimization across hierarchy boundaries (Created page with "Does Verific support design optimizations such as constant propagation and dead-code elimination across hierarchies? The optimization done during elaboration flow in Verific...")
- 16:15, 22 July 2019 (diff | hist) . . (+142) . . Main Page
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