User contributions
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- 10:49, 22 September 2016 (diff | hist) . . (+413) . . m Does Verific support XMR?
- 15:15, 4 August 2016 (diff | hist) . . (+5) . . m Main Page
- 15:14, 4 August 2016 (diff | hist) . . (+602) . . N Message handling (Created page with "'''Q: How do I upgrade/downgrade messages from Verific?''' For C++, use the following APIs: Message::SetMessageType() - Force a message type by message id Message::Ge...")
- 15:08, 4 August 2016 (diff | hist) . . (+71) . . m Main Page
- 15:33, 1 August 2016 (diff | hist) . . (+1) . . Constant expression replacement
- 15:32, 1 August 2016 (diff | hist) . . (+495) . . N Constant expression replacement (Created page with "'''Q: Does Verific replace constant expressions with their respective values?''' I have in my Verilog code: parameter size = 8; reg [size-1:0] foo; I expect the range...")
- 15:28, 1 August 2016 (diff | hist) . . (+121) . . m Main Page
- 10:43, 28 July 2016 (diff | hist) . . (-12) . . Remove Verific data structures
- 10:42, 28 July 2016 (diff | hist) . . (-32) . . m Remove Verific data structures
- 10:41, 28 July 2016 (diff | hist) . . (+24) . . m Remove Verific data structures
- 15:13, 27 July 2016 (diff | hist) . . (+11) . . m Main Page
- 15:12, 27 July 2016 (diff | hist) . . (+879) . . N SystemVerilog "std" package (Created page with "'''Q: Support for SystemVerilog semaphore/process/mailbox.''' When I analyzed my SystemVerilog file, Verific issued error message: test.sv(4): ERROR: process is not declare...")
- 15:05, 27 July 2016 (diff | hist) . . (+1) . . m Main Page
- 15:04, 27 July 2016 (diff | hist) . . (+97) . . m Main Page
- 15:02, 27 July 2016 (diff | hist) . . (+21) . . m Main Page
- 15:02, 27 July 2016 (diff | hist) . . (0) . . m Main Page
- 15:00, 27 July 2016 (diff | hist) . . (+65) . . m Main Page
- 14:46, 27 July 2016 (diff | hist) . . (-2) . . m Compile-time/run-time flags
- 14:40, 27 July 2016 (diff | hist) . . (+3) . . Compile-time/run-time flags
- 14:39, 27 July 2016 (diff | hist) . . (+790) . . N Compile-time/run-time flags (Created page with "'''Q: Are there options to control Verific software's behavior?''' There are compile-time flags and run-time flags to control Verific software's behavior. The compile-time f...")
- 14:29, 27 July 2016 (diff | hist) . . (+94) . . m Main Page
- 14:34, 26 July 2016 (diff | hist) . . (+1,053) . . N Included files associated with a Verilog source file (Created page with "'''Q: How do I get the list of included files associated with a Verilog source file?''' The main utility you require is: static Map *veri_file::GetIncludedFiles() ; It re...")
- 14:31, 26 July 2016 (diff | hist) . . (+140) . . m Main Page
- 14:01, 26 July 2016 (diff | hist) . . (+617) . . N Remove Verific data structures (Created page with "'''Q: How do I remove all Verific data structures in memory?''' To remove Verilog parsetree: veri_file::ResetParser(); To remove VHDL parsetree: vhdl_file::ResetPa...")
- 13:51, 26 July 2016 (diff | hist) . . (+94) . . m Main Page
- 13:15, 25 July 2016 (diff | hist) . . (+23) . . m How to get all Verilog files being analyzed
- 13:11, 25 July 2016 (diff | hist) . . (+107) . . m How to get all Verilog files being analyzed
- 18:10, 22 July 2016 (diff | hist) . . (+7) . . m Main Page
- 17:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 17:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 17:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 17:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 17:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 16:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 16:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 16:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 16:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 15:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 15:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 15:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 15:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 15:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 15:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 15:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 15:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 14:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
- 14:58, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 14:57, 22 July 2016 (diff | hist) . . (-1) . . m Design with System Verilog and Verilog 2001 files
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