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Showing below up to 20 results in range #21 to #40.

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21. How to get enums from Verilog parsetree‏‎ (10:36, 14 June 2017)
22. How to create a Netlist database from scratch (not from RTL input)‏‎ (17:10, 24 August 2018)
23. Support IEEE 1735 encryption standard‏‎ (11:58, 31 August 2018)
24. Top level module with interface ports‏‎ (17:41, 28 December 2018)
25. Design with System Verilog and Verilog 2001 files‏‎ (11:52, 12 February 2019)
26. Cross-reference between the original RTL files and the elaborated netlist‏‎ (15:30, 15 February 2019)
27. What languages can I use with Verific software?‏‎ (16:48, 21 February 2019)
28. Prettyprint to a string‏‎ (13:40, 1 March 2019)
29. Write out an encrypted netlist‏‎ (13:54, 1 March 2019)
30. Extract clock enable‏‎ (14:08, 1 March 2019)
31. Process -f file and explore the Netlist Database‏‎ (17:08, 1 March 2019)
32. Process -f file and explore the Netlist Database (py)‏‎ (17:14, 1 March 2019)
33. Process -f file and explore the Netlist Database (C++)‏‎ (17:17, 1 March 2019)
34. Retrieve package name for user-defined variable types‏‎ (12:03, 9 April 2019)
35. What are the data structures in Verific?‏‎ (17:25, 9 May 2019)
36. How to make lives easier‏‎ (18:14, 4 July 2019)
37. Type Range example‏‎ (16:41, 16 July 2019)
38. Test-based design modification‏‎ (14:00, 18 July 2019)
39. Logic optimization across hierarchy boundaries‏‎ (16:19, 22 July 2019)
40. Comment out a line using test-based design modification and parsetree modification‏‎ (12:21, 14 August 2019)

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