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- 16:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 16:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 16:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 16:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 16:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 16:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 15:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
- 15:58, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:57, 22 July 2016 (diff | hist) . . (-1) . . m Design with System Verilog and Verilog 2001 files
- 15:56, 22 July 2016 (diff | hist) . . (+875) . . N Design with System Verilog and Verilog 2001 files (Created page with "'''Q: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?''' The set of SystemVerilog construc...")
- 15:56, 22 July 2016 (diff | hist) . . (+17) . . m Main Page
- 15:51, 22 July 2016 (diff | hist) . . (-84) . . m Design with VHDL-1993 and VHDL-2008 files
- 15:51, 22 July 2016 (diff | hist) . . (+739) . . N Design with VHDL-1993 and VHDL-2008 files (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...")
- 15:50, 22 July 2016 (diff | hist) . . (-80) . . m Main Page
- 15:46, 22 July 2016 (diff | hist) . . (+9) . . m How to get module ports from Verilog parsetree (current)
- 15:45, 22 July 2016 (diff | hist) . . (+240) . . N Original RTL language (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...")
- 15:44, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
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